• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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    • 专利摘要:
    PURPOSE: A device for generating a test mode enable signal of a microcomputer is provided to generate the test mode enable signal by making the microcomputer enter a test mode when an external clock is normally operated. CONSTITUTION: A counter(10) generates the counter signals(C1-C4) counting the external clock signal(CLK_ext) received by a counting enable signal(EN). A stop signal generator generates the stop signals(S1-S4) having a short pulse by receiving the counting signal(C1-C4) from the counter(10). A multiplexer(30) selects and outputs one stop signal according to a control signal(CTL) by receiving the stop signals(S1-S4) from the stop signal generator(20). A latch and stop detector(40) generates the test mode enable signal(EN_test_mode) by detecting a folling span of the stop signal outputted from the multiplexer(30).
    公开号:KR20030000834A
    申请号:KR1020010036988
    申请日:2001-06-27
    公开日:2003-01-06
    发明作者:김병록
    申请人:주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    TEST MODE ENABLE SIGNAL GENERATOR FOR MICOM}
    [7] The present invention relates to a test mode enable signal generator of a microcomputer (hereinafter referred to as 'Micom'), and in particular, when the external clock is normally operated, the microcomputer enters the test mode. The present invention relates to a test mode enable signal generator of a microcomputer that generates an enable signal.
    [8] The test mode of the microcomputer is a test mode for verifying whether the microcomputer normally operates from the outside, and enters the test mode by the test mode enable signal EN_test_mode. FIG. 1 illustrates a configuration of a test mode enable signal generator of a conventional microcomputer that generates a test mode enable signal EN_test_mode.
    [9] As shown in FIG. 1, the test mode enable signal generator of the microcomputer according to the related art includes a counter circuit unit 1 that counts an external clock signal CLK_ext by a counting enable signal EN that is activated in a test mode. And a stop detector 2 for generating a test mode enable signal EN_test_mode after a polling period of the first counting signal generated from the counter circuit unit 1.
    [10] First, when entering the test mode, the counting enable signal EN is activated, and the counter circuit unit 1 operates after the falling edge of the counting enable signal EN to receive an external clock signal received from the outside. Generates a signal counting (CLK_ext). Next, in the stop circuit unit 2 that receives the counting signal generated from the counter circuit unit 1, a counting enable signal EN_test mode having a 'logic high' voltage after the falling edge of the first generated counting signal. Occurs.
    [11] On the other hand, since the entry of the test mode is only meaningful when the external clock signal CLK_ext operates normally when entering the test mode to verify whether the microcomputer operates normally, the test mode enable signal (after the external clock signal CLK_ext is stabilized) Test mode enable signal generator should be designed so that EN_test mode occurs.
    [12] However, the conventional microcomputer test mode enable signal generator generates an unconditionally counting enable signal EN_test mode at the falling edge of the first counting signal counting the external clock signal CLK_ext by the counting enable signal EN. Consists of. In general, the external clock signal CLK_ext needs to be adjusted by the system designer because the time to stabilize is uncertain. However, the conventional test mode enable signal generator generates a counting enable signal (EN_test mode) even when the external clock signal CLK_ext is unstable, consuming unnecessary current, degrading the overall operating speed of the microcomputer, and causing a malfunction. There was a problem.
    [13] Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to enable the test mode of the microcomputer to generate a test mode enable signal to enter the test mode when the external clock CLK_ext operates normally. To provide a signal generator.
    [1] 1 is a block diagram of a test mode enable signal generator of a microcomputer according to the prior art
    [2] 2 is a configuration diagram of a test mode enable signal generator of a microcomputer according to the present invention;
    [3] 3 is an operation timing diagram of each signal when entering a test mode according to the related art and the present invention.
    [4] Explanation of symbols on the main parts of the drawings
    [5] 10: counter 20: stop signal generator
    [6] 30: multiplexer section 40: latch and stop detection section
    [14] The test mode enable signal generator of the microcomputer according to the present invention for achieving the above object is a counter for generating a counter signal counting the number of the external clock signal received by the count enable signal is activated in the test mode, the counter; A stop signal generator for receiving N counting signals generated from a counter and generating N stop signals having a short pulse each time the counting signal is polled once; and N stops generated by the stop signal generator. A multiplexer unit for receiving a signal and outputting one stop signal selected by a control signal, and a latch and stop detector unit for detecting a polling interval of the stop signal output from the multiplexer unit and generating a test mode enable signal; It features.
    [15] The counter unit receives the counting enable signal as a clock signal as the input clock signal, and counts the signal counting the external clock signal after the counting enable signal is polled from 'high' to 'low'. The counting enable signal is polled from 'high' to 'low' by receiving the counting enable signal as the input signal and the counting enable signal as the clock signal CLK. Subsequently, the second counter unit outputs a signal counting the output signal of the first counter unit, and the output signal of the n-1 counter unit is received as a clock signal, and a counting enable signal is received as a clock signal. The n th counter unit outputs a signal counting the output signal of the n-th counter unit after being polled from 'high' to 'low'.
    [16] The first to nth counter parts may be configured as D flip-flops, respectively.
    [17] The stop signal generator is composed of N NAND gates that receive N counting signals generated from the counter or its inverted signal and generate a stop signal having a short pulse every time the N counting signals poll once. It features.
    [18] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    [19] In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.
    [20] FIG. 2 is a configuration diagram of a test mode enable signal generator of a microcomputer according to the present invention, and includes a counter signal (counting 4 external clock signals CLK_ext received by a counting enable signal EN activated in a test mode) When the counting signals C1 to C4 are polled once by receiving the counter unit 10 generating C1 to C4 and the counting signals C1 to C4 generated from the counter unit 10. A control signal is received by receiving a stop signal generator 20 for generating stop signals S1 to S4 having a short pulse every time, and stop signals S1 to S4 generated by the stop signal generator 20. The multiplexer unit 30 selects and outputs one stop signal by CTL, and detects a polling section of the stop signal output from the multiplexer unit 30 to detect a test mode enable signal EN_test_mode. The latch and stop detection part 40 which generate | occur | produces is provided.
    [21] The counter unit 10 receives an external clock signal CLK_ext as an input signal D, and counts the enable signal EN as a clock signal CLK, so that the counting enable signal EN is' high 'to' A first counter 11 for outputting a signal C1 counting the external clock signal CLK_ext after being polled low, and an output signal Q of the first counter 11 (D) after receiving the counting enable signal EN as the clock signal CLK and counting the enable signal EN from 'high' to 'low' after the counting of the first counter part 11. A second enable unit 12 which outputs a signal C2 counting the output signal C1 and an output signal C1 of the first counter unit 11 as an input signal D. After receiving the EN) as the clock signal CLK and counting the counting enable signal EN from 'high' to 'low', the output signal C1 of the first counter unit 11 is counted. The clock signal CLK is converted into a second enable unit 12 for outputting the set signal C2 and an output signal C2 of the second counter unit 12 as an input signal D. ) And outputs a signal C3 counting the output signal C2 of the second counter unit 12 after the counting enable signal EN is polled from 'high' to 'low'. The counting enable signal is received by receiving a counting enable signal EN as a clock signal CLK from the third counter 13 and the output signal C3 of the third counter 13 as an input signal D. And a fourth counter 14 for outputting a signal C4 counting the output signal C3 of the third counter 13 after (EN) is polled from 'high' to 'low'. .
    [22] The stop signal generator 20 receives the output signals C1-C4 of the first to third counters 11-13 and outputs a logically calculated signal S1 to the first NAND gate 51. And the inverted signal / C4 of the output signals C1-C3 of the first to third counter parts 11-13 and the output signal C4 of the fourth counter part 14 to be received and logic. A second NAND gate 52 for outputting the calculated signal S2, an output signal C1-C3 of the first to third counter units 11-13, and an output of the fourth counter unit 14; A third NAND gate 53 for receiving the inverted signal / C4 of the signal C4 and outputting a logically calculated signal S3, an output signal C1 of the first counter unit 11, and the Fourth NAND gate 54 for receiving the inverted signals / C2- / C4 of the output signals C2-C4 of the second to fourth counter units 12-14 and outputting a logically calculated signal S4. It is composed of
    [23] First, when entering the test mode, the counting enable signal EN is activated, and the counter unit 10 operates after the falling edge of the counting enable signal EN to receive an external clock signal received from the outside. Counter signals C1 to C4 counting (CLK_ext) are generated.
    [24] In the stop signal generator 20 that receives the counting signals C1 to C4 generated from the counter unit 10, a short pulse is generated whenever the counting signals C1 to C4 are polled once. To generate stop signals S1 to S4.
    [25] The multiplexer unit 30 receives the stop signals S1 to S4 generated by the stop signal generator 20 and selects and outputs one stop signal by the control signal CTL.
    [26] The latch and stop detector 40 detects a polling section of the stop signal output from the multiplexer 30 to generate a test mode enable signal EN_test_mode.
    [27] Figure 3 shows the operation timing of each signal when entering the test mode according to the prior art and the present invention.
    [28] Here, the waveforms (b) and (j) show the test mode entry method by the conventional test mode enable signal generator, and the waveforms (j)-(l) show the test mode entry method according to the present invention. will be. In the figure, waveforms (P0-P2) of (c)-(e) show the states of each port.
    [29] In general, in order to enter the test mode of the microcomputer, the test mode is entered into the test mode by the test mode enable signal EN (g) and the power supply voltage Vcc (a) and the port ce. It is shown in.
    [30] As shown, since the time for which the external clock signal CLK_ext is stabilized is uncertain, a number of conditions under which the counting signal is stopped are selected to be selectable according to the user's convenience. Accordingly, the test mode enable signal may be generated when the external clock signal CLK_ext operates normally by selecting the counted signal when the external clock signal CLK_ext is normally stabilized to generate the test mode enable signal.
    [31] As described above, according to the test mode enable signal generator of the microcomputer according to the present invention, a signal obtained by counting the external clock signal CLK_ext in multiple counts using a plurality of counter circuits is generated and stabilized using a multiplexer circuit. By selecting and outputting the external clock signal CLK_ext, a test mode enable signal can be generated when the external clock signal CLK_ext is normally operated. As a result, it is possible to reduce unnecessary current, improve the overall operating speed of the microcomputer, and perform stable test operation.
    [32] In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] In the test mode enable signal generator of Micom,
    A counter unit for generating a counter signal counting N external clock signals received by the counting enable signal activated in the test mode;
    A stop signal generator for receiving N counting signals generated from the counter and generating N stop signals having a short pulse each time the counting signal is polled once;
    A multiplexer unit for receiving the N stop signals generated by the stop signal generator and outputting one stop signal selected by a control signal;
    And a latch and stop detector for detecting a polling section of the stop signal output from the multiplexer to generate a test mode enable signal.
    [2" claim-type="Currently amended] The method of claim 1, wherein the counter unit,
    And receiving the counting enable signal as a clock signal and outputting a signal counting the external clock signal after the counting enable signal is polled from 'high' to 'low'. With 1 counter part,
    The output of the first counter unit after receiving the counting enable signal as the input signal, the counting enable signal as the clock signal CLK, and the counting enable signal is polled from 'high' to 'low'. A second counter unit for outputting a signal counting the signal;
    The output signal of the n-1 counter part after receiving the counting enable signal as a clock signal from the output signal of the n-1 counter part as a clock signal and the counting enable signal is polled from 'high' to 'low'. The test mode enable signal generator of the microcomputer, characterized in that consisting of the n-th counter for outputting the counted signal.
    [3" claim-type="Currently amended] The method of claim 2,
    And the first to nth counter units are configured as D flip-flops, respectively.
    [4" claim-type="Currently amended] The method of claim 1, wherein the stop signal generator,
    A microcomputer comprising N NAND gates that receive N counting signals generated from the counter or an inverted signal thereof and generate a stop signal having a short pulse every time the N counting signals are polled once. Test mode enable signal generator.
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    同族专利:
    公开号 | 公开日
    KR100384783B1|2003-05-23|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-06-27|Application filed by 주식회사 하이닉스반도체
    2001-06-27|Priority to KR10-2001-0036988A
    2003-01-06|Publication of KR20030000834A
    2003-05-23|Application granted
    2003-05-23|Publication of KR100384783B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR10-2001-0036988A|KR100384783B1|2001-06-27|2001-06-27|Test mode enable signal generator for micom|
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